1-mbit (64k x 16) static ram cy7c1021bn cy7c10211bn cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06494 rev. *a revised september 28, 2006 features ? temperature ranges ? commercial: 0c to 70c ? industrial: ?40c to 85c ? automotive-a: ?40c to 85c ? automotive-e: ?40c to 125c ?high speed ?t aa = 10 ns (commercial) ?t aa = 15 ns (automotive) ? cmos for optimum speed/power ? low active power ? 825 mw (max.) ? automatic power-down when deselected ? independent control of upper and lower bits ? available in pb free and non pb free 44-pin tsop ii and 44-pin 400-mil-wide soj functional description [1] the cy7c1021bn/cy7c10211bn is a high-performance cmos static ram organized as 65,536 words by 16 bits. this device has an automatic power-d own feature that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 1 through i/o 8 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 9 through i/o 16 ) is written into the location specified on the address pins (a 0 through a 15 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 1 to i/o 8 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 9 to i/o 16 . see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 1 through i/o 16 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). the cy7c1021bn/cy7c10211bn is available in standard 44-pin tsop type ii and 44-pin 400-mil-wide soj packages. customers should use part number cy7c10211bn when ordering parts with 10 ns t aa , and cy7c1021bn when ordering 12 ns and 15 ns t aa . note: 1. for best-practice recommendations, please refer to the cypress application note ?system design guidelines? on http://www.cypr ess.com logic block diagram 64k x 16 ram array i/o 1 ?i/o 8 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 a 15 512 x 2048 sense amps data in oe a 2 a 1 i/o 9 ?i/o 16 ce we ble bhe a 8 drivers we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view soj / tsop ii 12 13 41 44 43 42 16 15 29 30 v cc a 15 a 14 a 13 a 12 nc a 4 a 3 oe v ss a 5 i/o 16 a 2 ce i/o 3 i/o 1 i/o 2 bhe nc a 1 a 0 18 17 20 19 i/o 4 27 28 25 26 22 21 23 24 nc v ss i/o 7 i/o 5 i/o 6 i/o 8 a 6 a 7 ble v cc i/o 15 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 a 8 a 9 a 10 a 11 pin configurations [+] feedback [+] feedback
cy7c1021bn cy7c10211bn document #: 001-06494 rev. *a page 2 of 10 selection guide 7c10211b-10 7c1021b-12 7c1021b-15 maximum access time (ns) 10 12 15 maximum operating current (ma) com?l / ind?l 150 140 130 automotive-a 130 automotive-e 130 maximum cmos standby current (ma) com?l / ind?l 10 10 10 com?l / ind?l (l version) 0.5 0.5 0.5 automotive-a (l version) 0.5 automotive-e 15 pin definitions pin name soj, tsop?pin number i/o type description a 0 ?a 15 1?5,18?21, 24?27, 42?44 input address inputs used to select one of the address locations . i/o 1 ?i/o 16 7?10, 13?16, 29?32, 35?38 input/output bidirectional data i/o lines . used as input or output lines depending on operation. nc 22, 23, 28 no connect no connect s. not connected to the die. we 17 input/control write enable input, active low . when selected low, a write is conducted. when deselected high, a read is conducted. ce 6 input/control chip enable input, active low . when low, selects the chip. when high, deselects the chip. bhe , ble 40, 39 input/control byte write select inputs, active low . bhe controls i/o 16 ?i/o 9 , ble controls i/o 8 ?i/o 1 , . oe 41 input/control output enable, active low . controls the direction of the i/o pins. when low, the i/o pins are allo wed to behave as outputs. when deasserted high, i/o pins are tri- stated, and act as input data pins. v ss 12, 34 ground ground for the device . should be connected to ground of the system. v cc 11, 33 power supply power supply inputs to the device . [+] feedback [+] feedback
cy7c1021bn cy7c10211bn document #: 001-06494 rev. *a page 3 of 10 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc relative to gnd [2] .... ?0.5v to +7.0v dc voltage applied to outputs in high z state [2] ......................................?0.5v to v cc +0.5v dc input voltage [2] ...................................?0.5v to v cc +0.5v current into outputs (low) .... .....................................20 ma static discharge voltage......... .............. .............. ....... >2001v (per mil-std-883, method 3015) latch-up current ..................................................... >200 ma operating range range ambient temperature (t a ) [3] v cc commercial 0 c to +70 c 5v 10% industrial ?40 c to +85 c automotive-a ?40 c to +85 c automotive-e ?40 c to +125 c electrical characteristics over the operating range parameter description test conditions -10 -12 -15 unit min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.2 6.0 2.2 6.0 2.2 6.0 v v il input low voltage [2] ? 0.5 0.8 ?0.5 0.8 ?0.5 0.8 v i ix input leakage current gnd < v i < v cc com?l / ind?l ? 1 +1 ?1+1?1+1 a automotive-a ?1 +1 a automotive-e ?4 +4 a i oz output leakage current gnd < v i < v cc , output disabled com?l / ind?l ? 1 +1 ?1+1?1+1 a automotive-a ?1 +1 a automotive-e ?4 +4 a i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc com?l / ind?l 150 140 130 ma automotive-a 130 automotive-e 130 i sb1 automatic ce power-down current?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max com?l / ind?l 40 40 40 ma automotive-a 40 automotive-e 50 i sb2 automatic ce power-down current? cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 com?l / ind?l 10 10 10 ma com?l / ind?l (l) 0.5 0.5 0.5 automotive-a (l) 0.5 automotive-e 15 capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 8pf c out output capacitance 8 pf notes: 2. v il (min.) = ?2.0v and v ih (max) = v cc + 0.5v for pulse durations of less than 20 ns. 3. t a is the ?instant on? case temperature. 4. tested initially and after any design or process changes that may affect these parameters. [+] feedback [+] feedback
cy7c1021bn cy7c10211bn document #: 001-06494 rev. *a page 4 of 10 thermal resistance [4] parameter description test conditions 44-pin soj 44-pin tsop-ii unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 64.32 76.89 c/w jc thermal resistance (junction to case) 31.03 14.28 c/w ac test loads and waveforms switching characteristics [5] over the operating range parameter description 7c10211b-10 7c1021b-12 7c1021b-15 unit min. max. min. max. min. max. read cycle t rc read cycle time 10 12 15 ns t aa address to data valid 10 12 15 ns t oha data hold from address change 3 3 3 ns t ace ce low to data valid 10 12 15 ns t doe oe low to data valid 5 6 7 ns t lzoe oe low to low z [6] 000ns t hzoe oe high to high z [6, 7] 567ns t lzce ce low to low z [6] 333ns t hzce ce high to high z [6, 7] 567ns t pu ce low to power-up 0 0 0 ns t pd ce high to power-down 10 12 15 ns t dbe byte enable to data valid 5 6 7 ns t lzbe byte enable to low z 0 0 0 ns t hzbe byte disable to high z 5 6 7 ns notes: 5. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load c apacitance of 5 pf as in part (b) of ac te st loads. transition is measured 500 mv from steady-state voltage. 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) output r 481 ? r 481 ? r2 255 r2 255 167 equivalent to: thvenin equivalent 1.73v 30 pf rise time: 1 v/ns fall time: 1 v/ns 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) output r2 255 ? r2 255 ? 167 equivalent to: thvenin equivalent 30 pf rise time: 1 v/ns [+] feedback [+] feedback
cy7c1021bn cy7c10211bn document #: 001-06494 rev. *a page 5 of 10 write cycle [8] t wc write cycle time 10 12 15 ns t sce ce low to write end 8 9 10 ns t aw address set-up to write end 7 8 10 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns t sd data set-up to write end 5 6 8 ns t hd data hold from write end 0 0 0 ns t lzwe we high to low z [6] 333ns t hzwe we low to high z [6, 7] 567ns t bw byte enable to end of write 7 8 9 ns switching waveforms read cycle no. 1 [9, 10] read cycle no. 2 (oe controlled) [10, 11] notes: 8. the internal write time of the me mory is defined by the overlap of ce low, we low and bhe / ble low. ce , we and bhe / ble must be low to initiate a write, and the transition of these signals can terminate the wr ite. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. device is continuously selected. oe , ce , bhe and/or bhe = v il . 10. we is high for read cycle. switching characteristics [5] over the operating range (continued) parameter description 7c10211b-10 7c1021b-12 7c1021b-15 unit min. max. min. max. min. max. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high icc isb impedance data t dbe t lzbe t hzce i cc i sb address oe ce bhe ,ble out v cc supply current [+] feedback [+] feedback
cy7c1021bn cy7c10211bn document #: 001-06494 rev. *a page 6 of 10 write cycle no. 1 (ce controlled) [12, 13] write cycle no. 2 (ble or bhe controlled) notes: 11. address valid prior to or coincident with ce transition low. 12. data i/o is high impedance if oe or bhe and/or ble = v ih . 13. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw data address bhe , t ce address we ble i/o t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble we ce [+] feedback [+] feedback
cy7c1021bn cy7c10211bn document #: 001-06494 rev. *a page 7 of 10 write cycle no. 3 (we controlled, oe low) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe truth table ce oe we ble bhe i/o 1 ?i/o 8 i/o 9 ?i/o 16 mode power h x x x x high z high z power-down standby (i sb ) l l h l l data out data out read - all bits active (i cc ) l h data out high z read - lower bits only active (i cc ) h l high z data out read - upper bits only active (i cc ) l x l l l data in data in write - all bits active (i cc ) l h data in high z write - lower bits only active (i cc ) h l high z data in write - upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) l x x h h high z high z selected, outputs disabled active (i cc ) [+] feedback [+] feedback
cy7c1021bn cy7c10211bn document #: 001-06494 rev. *a page 8 of 10 ordering information speed (ns) ordering code package diagram package type operating range 10 CY7C10211BN-10ZXC 51-85087 44-pin tsop type ii commercial 12 cy7c1021bn-12vc 51-85082 44-pin (400-mil) molded soj commercial cy7c1021bn-12vxc 44-pin (400-mil) molded soj (pb-free) cy7c1021bn-12zc 51-85087 44-pin tsop type ii cy7c1021bn-12zxc 44-pin tsop type ii (pb-free) cy7c1021bn-12vi 51-85082 44-pin (400-mil) molded soj industrial cy7c1021bn-12vxi 44-pin (400-mil) molded soj (pb-free) 15 cy7c1021bn-15vc 51-85082 44-pin (400-mil) molded soj commercial cy7c1021bn-15vxc 44-pin (400-mil) molded soj (pb-free) cy7c1021bnl-15vxc 44-pin (400-mil) molded soj (pb-free) cy7c1021bn-15zc 51-85087 44-pin tsop type ii cy7c1021bn-15zxc 44-pin tsop type ii (pb-free) cy7c1021bnl-15zc 44-pin tsop type ii cy7c1021bnl-15zxc 44-pin tsop type ii (pb-free) cy7c1021bn-15vi 51-85082 44-pin (400-mil) molded soj industrial cy7c1021bn-15vxi 44-pin (400-mil) molded soj (pb-free) cy7c1021bn-15zi 51-85087 44-pin tsop type ii cy7c1021bnl-15zi 44-pin tsop type ii cy7c1021bn-15zxi 44-pin tsop type ii (pb-free) cy7c1021bnl-15zxi 44-pin tsop type ii (pb-free) cy7c1021bnl-15zsxa 51-85087 44-pin tsop type ii (pb-free) automotive-a cy7c1021bn-15vxe 51-85082 44-pin (400-mil) molded soj (pb-free) automotive-e cy7c1021bn-15zsxe 51-85087 44-pin tsop type ii (pb-free) package diagrams 1 22 23 44 0.395 0.405 0.435 0.445 1.120 1.130 0.045 max. 0.023 0.033 0.013 0.023 0.050 typ. 0.095 0.115 0.128 0.148 0.025 min. 0.082 min. 0-10 0.365 0.375 0.007 0.013 seating plane dimensions in inches min. max. 0.004 44-pin (400-mil) molded soj (51-85082) 51-85082-*b [+] feedback [+] feedback
cy7c1021bn cy7c10211bn document #: 001-06494 rev. *a page 9 of 10 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all products and company names mentioned in this docum ent may be the trademarks of their respective holders. package diagrams (continued) 44-pin tsop ii (51-85087) 51-85087-*a [+] feedback [+] feedback
cy7c1021bn cy7c10211bn document #: 001-06494 rev. *a page 10 of 10 document history page document title: cy7c1021bn/cy7c10211bn (64k x 16) static ram document number: 001-06494 rev. ecn no. issue date orig. of change description of change ** 423877 see ecn nxr new data sheet *a 505726 see ecn nxr removed i os parameter from dc electrical characteristics table. added automotive products updated ordering information table [+] feedback [+] feedback
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